| EXTERNAL PORTS |
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These are the external ports defined in the MHS file.
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Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK indicates Clock ports, (SIGIS = CLK)
INTR indicates Interrupt ports,(SIGIS = INTR)
RESET indicates Reset ports, (SIGIS = RST)
BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
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| # |
NAME |
DIR |
[LSB:MSB] |
SIG |
ATTRIBUTES |
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fpga_0_DIP_Switches_8Bit_GPIO_IO_pin |
IO |
0:7 |
fpga_0_DIP_Switches_8Bit_GPIO_IO |
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sys_clk_pin |
I |
1 |
dcm_clk_s |
CLK |
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sys_rst_pin |
I |
1 |
sys_rst_s |
RESET |
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REFCLK_N_IN_pin |
I |
1 |
REFCLK_N_IN |
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REFCLK_P_IN_pin |
I |
1 |
REFCLK_P_IN |
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EMAC_READY_pin |
O |
1 |
EMAC_READY |
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PHY_RESET_0_pin |
O |
1 |
PHY_RESET_0 |
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HARD_ERROR_pin |
O |
1 |
HARD_ERROR |
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SOFT_ERROR_pin |
O |
1 |
SOFT_ERROR |
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FRAME_ERROR_pin |
O |
1 |
FRAME_ERROR |
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LANE_UP_pin |
O |
1 |
LANE_UP |
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CHANNEL_UP_pin |
O |
1 |
CHANNEL_UP |
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LCD_IO_pin |
IO |
0:6 |
LCD_IO |
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