EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0A fpga_0_DIP_Switches_8Bit_GPIO_IO_pin IO 0:7 fpga_0_DIP_Switches_8Bit_GPIO_IO 1B fpga_0_LEDs_8Bit_GPIO_IO_pin IO 0:7 fpga_0_LEDs_8Bit_GPIO_IO 2C fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 3C fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 4D sys_clk_pin I 1 dcm_clk_s  CLK  5E sys_rst_pin I 1 sys_rst_s  RESET