EXTERNAL PORTS

These are the external ports defined in the MHS file.

Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)

# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0A fpga_0_RS232_Uart_1_RX_pin I 1 fpga_0_RS232_Uart_1_RX 1A fpga_0_RS232_Uart_1_TX_pin O 1 fpga_0_RS232_Uart_1_TX 2B sys_clk_pin I 1 dcm_clk_s  CLK  3B fpga_0_net_gnd_1_pin O 1 net_gnd 4B fpga_0_net_gnd_2_pin O 1 net_gnd 5B fpga_0_net_gnd_3_pin O 1 net_gnd 6B fpga_0_net_gnd_4_pin O 1 net_gnd 7B fpga_0_net_gnd_5_pin O 1 net_gnd 8B fpga_0_net_gnd_6_pin O 1 net_gnd 9B fpga_0_net_gnd_pin O 1 net_gnd 10C fpga_0_onewire_0_ONEWIRE_DQ IO 1 fpga_0_onewire_0_ONEWIRE_DQ 11D sys_rst_pin I 1 sys_rst_s  RESET